Labs

A number of labs are described in this section of the course. These help you train the theoretical part of this course. Some exercises are simple and the correct solution is provided on this website. Other exercises require you to write code and simulate it.

You can either use Simulation software for this (for example: QuestaSim) or you can use an online platform (for example: https://www.edaplayground.com/)

QuestaSim - Example: an inverter

The exercises in this course are run using Mentor’s Questa Sim. For those unfamiliar with this tool, we first give an example using an inverter. Feel free to make a folder in the home directory in which you will do exercises during this course.

1. Write the HDL for the DUT and the test

The DUT is written in a file: inverter.sv 
  `timescale 1ns / 100ps;

  module inverter (A, B);
    input A;
    output B;

    assign B = ~A;
  endmodule
  ```
The test is written in a file: inverter_tb.sv 
  `timescale 1ns / 100ps;

  module inverter_tb();
    logic in, out;
    inverter my_inverter_inst(in,out);

    initial
    begin
      in = 0;
      #10 in = 1;
      #20 in = 0;
    end
  endmodule

2. Make a library work

QuestaSim requires a library directory to store information about your project. Such a directory, e.g. named “work”, can be generated by the following command:

vlib work

3. Compiling

Before the simulation can be run, both the RTL files and the test files need to be compiled. This can also be done directly from the command line interface:

vlog -sv inverter.sv
vlog -sv inverter_tb.sv

or, compiling multiple files in one command:

vlog -sv src_rtl/inverter.sv src_tb/inverter_tb.sv

This typically is the point at which syntax errors are found and displayed. For example:

vlog -sv inverter.sv
-- Compiling module inverter
** Error: (vlog-13069) inverter.sv(7): near ";": syntax error,
unexpected ';'.
-- Compiling module inverter_tb
End time: 09:54:56 on May 22,2018, Elapsed time: 0:00:00
Errors: 1, Warnings: 0

Note the -sv option: this option enables the SystemVerilog features and keywords.

4. The simulator

The simulator can be used with a command line interface, or with a graphical user interface (GUI). To use the command line mode, an option “-c” needs to be given.

vsim -c

For the graphical user interface no additional argument is required. The command line interface works (more or less) the same as the “Transcript” window in the graphical user interface.

In the GUI waveforms can be examined. To do this, signals have to be added from the “Objects” window by right-clicking on the signal name and selecting “Add Wave”. Another way of achieving this is through the “Transcript” window.

The “Transcript” window offers you an interface to use the tool by typing commands. A summarised list of useful commands is given on the cheat page.

do files

When you’re comfortable with the simulator, clicking with a mouse becomes a bit slow. Using the command-line interface can save you a lot of time. However, repeating a lot of typing is cumbersome.

To be super efficient, aliases can be used. For example, if you have a 100-line long do file that is called doEverythingForMeAutomagically.do, typing that file name can be improved upon. For those thrill-seekers, the alias command can be nice:

alias e “do doEverythingForMeAutomagically.do”

Now you only have to press two buttons: e and enter.

Get comfortable with the simulator

Try to get the simulation going for the inverter.