0 Introduction
000 Introduction
001 Organisation
002 Lab
1 Getting your feet wet
100 ALU
101 Testing
102 SystemVerilog
103 Interfaces
104 Hello world
105 Assignment 1
2 Adding some registers
201 Register file
202 Updating test
203 Practice
3 Climbing the OO ladder
301 Layered testbench
302 Adding a monitor
303 Join or fail
304 Transactions
305 Mailboxes
306 Assignment 2
307 Checker & scoreboard
308 Golden reference
4 Randomisation
401 Randomisation
402 Constraints
403 DP and CP
404 Assignment 3
5 Coverage
501 Coverage
502 Functional coverage
503 Cross coverage
504 More on bins
505 Assignment 4
6 Assertions
601 Assertions
602 Sequences
603 Implications
7 Project
8 Final remarks
801 Final remarks
Appendices
QuestaSim Commanline Cheats
More
ECTS Sheet
Toledo
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Chip Design and Verification
> 6 Assertions
Assertions
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Brett Sayles
