Multiple clocks
A lot of designs, today, have multiple clock signals. Even in our rather simple exercise a second 100 kHZ pops up. When multiple clock signals are present, special attention is required !!
Clock domain crossing
All the components that are synchronised to one clock form a group that is called a clock domain. In our example we have two clock domains (the 100 MHz and the 100 kHz).
When signals switch from one clock domain to the other, bad stuff can happen. There is an EE Times article that explains the possible issues (and fixes) very well. The three main issues with clock domain crossing are:
- Metastability: a signal which between a logical high and logical low level
- Data loss: a bit of information (literally: a bit) is lost
- Data incoherency: a bit in a word is delayed, for example
The aforementioned article presents a nice flow chart that helps you to clean your design
Flow chart to clean your design for clock domain crossing signals
During Jo Vliegen his final two job interviews, he was asked to explain the threats in and solutions for clock domain crossing.
Suggested approach
Not to complicate the design too much, it is best to keep as much of the design as possible in a single clock domain. One fact which we can rely on is that the frequencies of both clocks is fixed, their phase shift, however is unknown.
- Synchronous clocks ? yes ( 10 ns * 1000 = 10 µs )
- Clock edges can be close ? yes
- Synchroniser present ?no
- action: add synchroniser
- Separately synchronised converging signals ? no (our 2 wires are synchronised on the same clock)
- Clock edges close for continuous cycles ? no (because the big difference in frequencies)
- Fast to slow crossing ? no
