2.3 - One more thing ...
The implementation of the RISC-V that is used in this course, is a single-cycle implementation. Nonetheless, in earlier courses you might have already seen how pipelining has a huge effect on the implementation. The major advantage of a single-cycle implementation is that it is rather simple to understand and implement. The major drawback is that is not as performant, but it going to get even worse.
In the previous section, it was shown that the BRAM needs at least one clock cycle to read from the memory. Unfortunately, this does not work for a single cycle implementation.
The easiest “fix” for this is disable the processor every other cycle.
Even from the width of waveforms above, the issue with this fix can be clearly seen: the latency is doubled!
However, consider this …
One clock cycle had to be artificially added for the instruction memory. If the instruction also involves the data memory one more clock cycle needs to be added.
