The final push in these lab sessions is to apply what has been seen in previous weeks. The examples started on the ALU only and not for long the registerfile of the processor was added. For the project, the DUT is extended again. The added feature is that the load operations are now (almost completely) supported .
For the project, this implementation has to be verified.
The criteria on what has to be checked, how these are to be checked, and how thoroughly, … it’s all up to you!!
Roughly 25% of all the available 8-bit instructions are load-instructions. These instructions have 8 target: regA, regB, regC, regD, regE, regH, regL, and the indirectly addresses position on address HL. Because every target can be loaded with the value of any other target, this gives 8*(8-1) = 56 load instructions. Additionally, there is an option for directly loading an 8-bit value into a target. With these additional 8 instructions, there are 64 load operations.
REDO IMAGE