Assignment 1
The first assignment is to write, analogous to the given example, a simple testbench. The DUT is the ALU that was seen earlier.
You only need to test the addition: Keep one operand fixed to 0x01 and have the other operand loop over all 256 possible values.
After this chapter you should …
- ... have your development and simulation environment set up (efficiently)
- ... have gotten your hands dirty
- ... have some experience using mixing languages
- ... have a basic understanding of how SystemVerilog communicates with the hardware