These series of lab sessions will introduce you to SystemVerilog. Although this series will be taught during application colleges, the interested student can proceed at his/her own pace. If you are intrigued by the exercises, of if you prefer to continue working while the mindset is focused on the topic, you should find it possible to continue at a faster pace.
If you have any question, suggestion, or problem with these labs, the forum on Toledo is your place-to-go. We encourage team spirit and the idea of overcoming this challenge together.
The lab sessions will focus on the following topics:
Throughout the chapter very short exercises might be present, but you are encouraged to try out different snippets of code that are presented. There is a big difference between seeing-and-(hopefully-)understanding code, and writing it yourself.
At the end of every chapter, there is an assignment. These assignments should be made individually and are the be handed in through the Toledo platform.