Chip Design and Verification
These webpages will guide you through the lab sessions of Chip Design and Verification. The focus in these labs lies in Verification, using SystemVerilog.
In the first section Getting your feet wet the basic concepts of SystemVerilog are explained. The next section Adding some registers does as it says: it adds registers to the design. Climbing the OO ladder handles how the object-oriented nature of SystemVerilog is organised.
After sowing, it becomes time to reap. This is done with Randomisation and Coverage. Finally, the top of the iceberg is scratched on Assertions.
Armed with those concepts, it’s time to put it in actions in the Project.
If you have any questions or if you want to discuss certain subjects (with other students or with us), please visit the Toledo Forum.